37 lines
685 B
Systemverilog
37 lines
685 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class RandomValue;
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rand int value;
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constraint small_int_c {
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value < 10;
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}
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task disable_val();
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value.rand_mode(0);
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endtask
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endclass
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class Base;
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endclass
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class Foo extends Base;
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rand RandomValue v = new;
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endclass
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module t;
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Base b;
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initial begin
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Foo d = new;
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b = d;
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d.v.disable_val();
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d.v.value = 11;
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if (bit'(b.randomize())) $stop;
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if (d.v.value != 11) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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