69 lines
1.4 KiB
Systemverilog
69 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// The number of clocks in the clock vector
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localparam int N = 5;
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`ifdef LIB_CREATE
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// This is built with --lib-create
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module sub(
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input logic [N-1:0] clkvec,
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output logic [7:0] cnt[N]
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);
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for (genvar i = 0; i < N; ++i) begin : GEN
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logic [7:0] counter = 8'd0;
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always @(posedge clkvec[i]) counter <= counter + 8'd1;
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assign cnt[i] = counter;
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end
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endmodule
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`else
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// This is built as the top level
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module top;
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logic [N-1:0] clkvec = N'(0);
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logic [7:0] cnt [N];
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// Generate clocks by rotation
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always #5 clkvec = {clkvec[N-2:0], clkvec[N-1] | ~|clkvec};
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sub sub_i(clkvec, cnt);
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always @(clkvec) begin
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#1;
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$write("%10t %05b", $time, clkvec);
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for (int i = N-1; i >= 0; --i) begin
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$write(" cnt[%0d]=%02d", i, cnt[i]);
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end
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$write("\n");
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// No counter should reach above 10
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for (int i = 0; i < N; ++i) begin
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if (cnt[i] > 10) $stop;
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end
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// Conclude when all counters reach 10
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begin
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static bit done = 1'b1;
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for (int i = 0; i < N; ++i) begin
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if (cnt[i] != 10) done = 1'b0;
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end
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if (done) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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`endif
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