35 lines
856 B
Systemverilog
35 lines
856 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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package uvm_pkg;
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class uvm_reg_sequence #(
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type BASE = int
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);
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typedef enum {
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LOCAL = 2,
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UPSTREAM = 3
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} seq_parent_e;
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endclass
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endpackage
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module t;
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import uvm_pkg::*;
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class test_seq extends uvm_reg_sequence;
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endclass
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initial begin
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test_seq c;
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c = new;
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`checkd(c.LOCAL, 2);
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`checkd(c.UPSTREAM, 3);
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$finish;
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end
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endmodule
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