47 lines
1.0 KiB
Systemverilog
47 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t;
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import "DPI-C" context function int dpii_add();
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virtual class uvm_sequence #(
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type RSP = int
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);
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endclass
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class Cls extends uvm_sequence #();
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virtual function void check_reg();
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int paths[$];
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int i;
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paths.push_back(1);
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paths.push_back(2);
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foreach (paths[p]) begin
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i = dpii_add();
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end
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endfunction
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endclass
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initial begin
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Cls c;
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int i;
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c = new;
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i = dpii_add();
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`checkd(i, 1);
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c.check_reg();
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i = dpii_add();
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`checkd(i, 4);
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$finish;
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end
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endmodule
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