43 lines
1.2 KiB
Systemverilog
43 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Passing a real interface array as a class new() argument bound to a
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// virtual interface array formal parameter. Exercises the cell dearrayer's
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// orphan-VarRef fixup in V3Inst.
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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// verilog_format: on
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interface AXI_BUS_DV;
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endinterface
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package tb_axi_xbar_pkg;
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class axi_xbar_monitor #(
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parameter int unsigned NoMasters
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);
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int captured_count;
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function new(virtual AXI_BUS_DV axi_masters_vif[NoMasters-1:0]);
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captured_count = NoMasters;
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endfunction
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endclass
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endpackage
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module t;
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localparam int unsigned TbNumMasters = 32'd6;
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AXI_BUS_DV master_monitor_dv[TbNumMasters-1:0] ();
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initial begin
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static tb_axi_xbar_pkg::axi_xbar_monitor #(.NoMasters(TbNumMasters))
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monitor = new(master_monitor_dv);
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`checkh(monitor.captured_count, 32'd6);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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