54 lines
1.4 KiB
Systemverilog
54 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Multi-dimensional interface instance arrays: minimal 2D reproducer.
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// Exercises declaration, dotted access, multi-dim port connection and
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// VCD-relevant naming.
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interface simple_if;
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logic [7:0] data;
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endinterface
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module t;
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localparam int A = 2;
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localparam int B = 3;
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simple_if bus[A-1:0][B-1:0] ();
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genvar gi, gj;
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generate
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for (gi = 0; gi < A; gi++) begin : g_a
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for (gj = 0; gj < B; gj++) begin : g_b
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initial bus[gi][gj].data = 8'(gi * B + gj + 1);
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end
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end
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endgenerate
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// Runtime check via a chk array populated by the same genvar generate block.
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logic [7:0] chk[A-1:0][B-1:0];
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generate
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for (gi = 0; gi < A; gi++) begin : g_a_chk
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for (gj = 0; gj < B; gj++) begin : g_b_chk
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always_comb chk[gi][gj] = bus[gi][gj].data;
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end
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end
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endgenerate
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initial begin
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#1;
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for (int i = 0; i < A; i++) begin
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for (int j = 0; j < B; j++) begin
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if (chk[i][j] !== 8'(i * B + j + 1)) begin
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$write("%%Error: bus[%0d][%0d].data=%0d expected %0d\n", i, j, chk[i][j], i * B + j + 1);
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$stop;
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end
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end
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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