14 lines
343 B
Systemverilog
14 lines
343 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Verify multi-dim gate primitive arrays are rejected.
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module t;
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wire a, b;
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wire [1:0][1:0] y;
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and g[1:0][1:0] (y, a, b);
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endmodule
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