49 lines
1.1 KiB
Systemverilog
49 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: same-state multi-candidate FSM error test
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input logic clk,
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input logic rst
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);
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typedef enum logic [1:0] {
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S0,
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S1,
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S2
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} state_t;
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state_t state;
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state_t state_if;
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// This is intentionally non-idiomatic RTL. The detector sees one supported
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// candidate in the reset-if else branch and a second supported top-level
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// case on the same state variable. That same-state duplicate is rejected.
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always_ff @(posedge clk) begin
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if (rst) begin
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state <= S0;
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end
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else begin
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case (state)
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S0: state <= S1;
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default: ;
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endcase
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end
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case (state)
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S1: state <= S2;
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default: ;
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endcase
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end
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always_ff @(posedge clk) begin
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if (state_if == S0) state_if <= S1;
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else if (state_if == S1) state_if <= S0;
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if (state_if == S1) state_if <= S2;
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else if (state_if == S2) state_if <= S1;
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end
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endmodule
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