76 lines
1.5 KiB
Systemverilog
76 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Coverage per-instance hierarchy for duplicate module instances
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module child #(
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parameter int WIDTH = 1
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) (
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input clk,
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input en
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);
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`ifdef INLINE_CHILD //verilator inline_module
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`else //verilator no_inline_module
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`endif
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reg [WIDTH-1:0] count = '0;
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always @(posedge clk) begin
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if (en) begin
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count <= count + 1'b1;
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end else begin
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count <= count;
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end
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end
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endmodule
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module t (
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input clk
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);
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reg [3:0] cyc = 0;
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// Over 9 clock edges, u_a.en is true for cyc 0..3, so u_a should report
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// if coverage of 4, else coverage of 5, and line coverage of 9.
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child u_a (
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.clk(clk),
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.en(cyc < 4)
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);
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// u_b.en is true only for cyc 0, so u_b should report if coverage of 1,
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// else coverage of 8, and line coverage of 9.
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child u_b (
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.clk(clk),
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.en(cyc == 0)
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);
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// Parameterized u_wide should preserve a useful per-instance hierarchy and
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// parameter-specialized coverage bucket for downstream coverage tools.
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child #(
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.WIDTH(3)
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) u_wide (
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.clk(clk),
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.en(cyc < 2)
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);
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always @(posedge clk) begin
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cyc <= cyc + 1'b1;
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end
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endmodule
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module tb;
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reg clk = 0;
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t dut (
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.clk(clk)
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);
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always #1 clk = !clk;
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always @(posedge clk) begin
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if (dut.cyc == 8) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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