24 lines
505 B
Systemverilog
24 lines
505 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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module t;
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bit clk;
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bit a;
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bit b;
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property p_nc_range;
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@(posedge clk) a |-> b [= 1: 2];
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endproperty
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property p_nc_lhs_range;
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@(posedge clk) a [= 1: 2] |-> b;
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endproperty
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a_nc_range :
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assert property (p_nc_range);
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a_nc_lhs_range :
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assert property (p_nc_lhs_range);
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endmodule
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