77 lines
1.9 KiB
Systemverilog
77 lines
1.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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package pkg;
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typedef struct {
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logic [7:0] value;
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} field_t;
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typedef struct {
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field_t f0;
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field_t f1;
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} reg_t;
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typedef struct {
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reg_t R0;
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reg_t R1;
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reg_t R2;
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} hwif_t;
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endpackage
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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import pkg::*;
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hwif_t hwif_in;
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hwif_t hwif_out;
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hwif_t storage;
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integer cyc = 0;
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always_ff @(posedge clk) begin
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storage.R0.f0.value <= hwif_in.R0.f0.value;
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storage.R0.f1.value <= hwif_in.R0.f1.value;
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storage.R1.f0.value <= hwif_in.R1.f0.value;
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storage.R1.f1.value <= hwif_in.R1.f1.value;
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storage.R2.f0.value <= hwif_in.R2.f0.value;
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storage.R2.f1.value <= hwif_in.R2.f1.value;
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end
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always_comb begin
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hwif_out.R0.f0.value = storage.R0.f0.value;
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hwif_out.R0.f1.value = storage.R0.f1.value;
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hwif_out.R1.f0.value = storage.R1.f0.value;
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hwif_out.R1.f1.value = storage.R1.f1.value;
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hwif_out.R2.f0.value = storage.R2.f0.value;
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hwif_out.R2.f1.value = storage.R2.f1.value;
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end
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 0) begin
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hwif_in.R0.f0.value <= 8'h11;
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hwif_in.R0.f1.value <= 8'h22;
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hwif_in.R1.f0.value <= 8'h33;
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hwif_in.R1.f1.value <= 8'h44;
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hwif_in.R2.f0.value <= 8'h55;
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hwif_in.R2.f1.value <= 8'h66;
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end
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else if (cyc == 3) begin
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if (hwif_out.R0.f0.value !== 8'h11) $stop;
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if (hwif_out.R0.f1.value !== 8'h22) $stop;
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if (hwif_out.R1.f0.value !== 8'h33) $stop;
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if (hwif_out.R1.f1.value !== 8'h44) $stop;
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if (hwif_out.R2.f0.value !== 8'h55) $stop;
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if (hwif_out.R2.f1.value !== 8'h66) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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