41 lines
944 B
Systemverilog
41 lines
944 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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`ifdef VERILATOR
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// The '$c(1)' is there to prevent inlining of the signal by V3Gate.
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`define IMPURE_ONE ($c(1))
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`else
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// Use standard $random. The chance of getting 2 consecutive zeroes is negligible.
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`define IMPURE_ONE (|($random | $random))
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`endif
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module t;
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bit [2:0] y;
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bit [2:0] z;
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assign z[0] = 1'b1;
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assign z[1] = !(y[0]);
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assign z[2] = !(|y[1:0]);
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class Foo;
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bit foo;
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task run();
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foo = `IMPURE_ONE;
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if (z !== 3'b001) begin
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$error("Failed: got %0b, expected %0b", z, 3'b001);
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end
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if (foo != 1'b1) $stop;
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endtask
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endclass
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Foo test;
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initial begin
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static Foo foo = new;
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#10 y = 3'b111;
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#1 foo.run();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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