75 lines
1.9 KiB
Systemverilog
75 lines
1.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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// Issue #7203: virtual interface select from sub-interface instance.
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// The original reproducer: vip_agent holds vip_vif; vip_driver selects
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// agent.vif.tx (a vip_tx_if sub-interface) into tx_vif.
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interface vip_tx_if (
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output reg Tx
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);
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endinterface
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interface vip_if (
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output reg Tx
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);
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vip_tx_if tx (Tx);
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endinterface
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package vip_pkg;
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typedef virtual vip_if vip_vif;
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typedef virtual vip_tx_if vip_tx_vif;
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class vip_agent;
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vip_vif vif;
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endclass
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class vip_driver;
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vip_vif vif;
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vip_tx_vif tx_vif;
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virtual function void build_phase(vip_agent agent);
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// Sub-interface select: dtype(agent.vif) -> vip_vif -> vip_if
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vif = agent.vif;
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tx_vif = agent.vif.tx;
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endfunction
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// Chained member access through sub-interface
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virtual function void drive(logic val);
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vif.tx.Tx = val;
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endfunction
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endclass
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endpackage
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module t;
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logic wire_Tx;
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vip_if vif_inst (.Tx(wire_Tx));
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initial begin
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automatic vip_pkg::vip_agent agent = new;
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automatic vip_pkg::vip_driver driver = new;
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agent.vif = vif_inst;
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driver.vif = vif_inst;
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// Test 1 (issue reproducer): sub-interface select compiles and runs
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driver.build_phase(agent);
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// Test 2: tx_vif now points to the sub-interface; write through it
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driver.tx_vif.Tx = 1'b1;
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`checkd(wire_Tx, 1'b1)
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// Test 3: chained member write through virtual interface
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driver.drive(1'b0);
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`checkd(wire_Tx, 1'b0)
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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