26 lines
533 B
Systemverilog
26 lines
533 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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bit clk = 1'b0;
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always #5 clk = ~clk;
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initial begin
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#300;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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// Complicated way to write constant 0 that only Dfg can decipher
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wire [1:0] constant = 2'b0 ^ (({2{clk}} & ~{2{clk}}));
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always @(posedge constant[0]) begin
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$stop;
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end
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endmodule
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