80 lines
1.2 KiB
Systemverilog
80 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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class msg;
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string context_name;
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function void set_context(string name);
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context_name = name;
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endfunction
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endclass
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package helper_pkg;
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int package_counter;
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function void bump();
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package_counter++;
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endfunction
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endpackage
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interface intf(output logic a, output logic b);
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msg m;
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event e;
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task go();
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helper_pkg::package_counter++;
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go_helper();
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go_helper();
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endtask
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task go_helper();
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// verilator no_inline_task
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m.set_context("go_helper");
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helper_pkg::bump();
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-> e;
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a <= 1;
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endtask
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endinterface
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class driver;
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virtual intf vif;
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function new(virtual intf vif);
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this.vif = vif;
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endfunction
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task go();
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vif.go();
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endtask
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endclass
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module t;
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wire a;
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wire b;
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virtual intf vif;
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intf i(a, b);
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initial begin
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driver d;
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vif = t.i;
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t.i.m = new;
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d = new(t.i);
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d.go();
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end
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always @(posedge a) begin
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vif.b <= 1;
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end
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always @(*) begin
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if (a && b) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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