mirror of
https://github.com/verilator/verilator.git
synced 2026-10-06 10:03:44 +02:00
Geza Lore
8546d5db06
The loops modelling the SystemVerilog scheduling regions are no longer generated. They now live in 'VerilatedEvalLoop' in the runtime library. The generated model holds one as a member, passing itself to it, and exposes each evaluation entry point to it as a pure virtual method on VerilatedModel. The model's 'eval' and 'eval_step' remain the top level entry points, and are backward compatible. V3Sched no longer emits '_eval' or '_eval_settle', etc.. Instead every evaluation entry point called from the runtime is enumerated by 'VEval', Scheduling creates all entry points, for all scheduling regions, even if they are empty, and the runtime eval loop calls everything unconditionally. If regions are empty, this is simply a call to an empty function. This will hurt performance on very small models, but should not be noticeable on anything meaningful, so it is likely best to keep to reduce complexity. A scheduling entry points evaluate a single iteration and returns whether it did any work, they are effectively the previous `_eval_phase_*` functions.
57 lines
1.9 KiB
Python
Executable File
57 lines
1.9 KiB
Python
Executable File
#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2025 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.top_filename = "t/t_lib_prot.v"
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if test.benchmark:
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test.sim_time = test.benchmark * 100
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trace_opt = "" if re.search(r'--no-trace', ' '.join(test.driver_verilator_flags)) else "-trace"
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secret_prefix = "secret"
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secret_dir = test.obj_dir + "/" + secret_prefix
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test.mkdir_ok(secret_dir)
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# Compile the lib
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test.run(logfile=secret_dir + "/vlt_compile.log",
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cmd=[
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"perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", '--no-timing', "--prof-exec",
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trace_opt, "--prefix", "Vt_lib_prot_secret", "-cc", "-Mdir", secret_dir,
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"--lib-create", secret_prefix, "t/t_lib_prot_secret.v"
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],
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verilator_run=True)
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test.run(logfile=secret_dir + "/secret_gcc.log",
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cmd=[os.environ["MAKE"], "-C", secret_dir, "-f", "Vt_lib_prot_secret.mk"])
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# Compile the simulator
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test.compile(verilator_flags2=[
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'--no-timing', "--prof-exec", trace_opt, "-LDFLAGS", secret_prefix +
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"/libsecret.a", secret_dir + "/secret.sv"
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])
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# Run with profiling
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test.execute(all_run_flags=[
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"+verilator+prof+exec+start+0", " +verilator+prof+exec+window+10",
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" +verilator+prof+exec+file+" + test.obj_dir + "/profile_exec.dat"
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])
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# Generate report
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gantt_log = test.obj_dir + "/gantt.log"
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test.run(cmd=[
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os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt", test.obj_dir +
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"/profile_exec.dat", "--vcd " + test.obj_dir + "/profile_exec.vcd", "| tee " + gantt_log
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])
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# Check both lib and sim are present
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test.file_grep_count(gantt_log, r'\|\s+[1-9][0-9]*\s+\|\s+[0-9.]+\s+\|\s+eval', 2)
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test.passes()
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