mirror of
https://github.com/verilator/verilator.git
synced 2026-10-06 10:03:44 +02:00
Geza Lore
976ec63531
Arrays of module instances are now expanded into their element cells during elaboration in V3Param, instead of after V3Width in V3Inst::dearrayAll. Element cells are named as before (name__BRA__i__KET__...), are ordered from the left index to the right index, and hierarchical references to them resolve in linkDotParamed. Arrays of interface instances are still expanded by V3Inst. They will move in a follow up patch. Algorithmically: - V3Praram replaces an arrayed AstCell, with a scalar Cell for each element. linkDotParamed can resolve against these as normal. - V3Width then fixes up the AstPins of each expanded Cell according to the LRM rules. Either leaving the alone to connect to all instances, or inserting ArraySel/Sel to connect the relevant part to the relevant instance. Partial #2675
36 lines
915 B
Systemverilog
36 lines
915 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain.
|
|
// SPDX-FileCopyrightText: 2005 Wilson Snyder
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
module t;
|
|
|
|
wire [7:0] bitout;
|
|
reg [7:0] allbits;
|
|
reg [7:0] onebit;
|
|
reg [8:0] onebitbad; // Wrongly sized
|
|
|
|
sub sub [7:0] (allbits, onebitbad, bitout);
|
|
|
|
// This is ok.
|
|
wire [9:8] b;
|
|
wire [1:0] c;
|
|
sub sub2 [9:8] (allbits,b,c);
|
|
|
|
// Multi-dimensional, 6 elements
|
|
reg [6:0] sixbitbad; // Wrongly sized
|
|
wire [5:0] sixbitout;
|
|
sub sub3 [1:0][2:0] (allbits, sixbitbad, sixbitout);
|
|
|
|
// Unpacked connection with fewer unpacked dimensions than the instance array
|
|
reg onebits2[1:0];
|
|
wire [5:0] sixbitout2;
|
|
sub sub5 [1:0][2:0] (allbits, onebits2, sixbitout2);
|
|
|
|
endmodule
|
|
|
|
module sub (input [7:0] allbits, input onebit, output bitout);
|
|
assign bitout = onebit ^ (^ allbits);
|
|
endmodule
|