25 lines
541 B
Systemverilog
25 lines
541 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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class Sleeper;
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task sleep;
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event e;
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fork
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@e;
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#1 ->e;
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join;
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endtask
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endclass
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initial begin
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Sleeper sleeper = new;
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sleeper.sleep;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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