20 lines
359 B
Systemverilog
20 lines
359 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module A (
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output [2:0] Y
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);
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endmodule
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module B;
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wire [2:0] w1;
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wire w2;
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A A (
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.Y({ w1[2], w1[0], w2 })
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);
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assign w1[1] = w1[2];
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endmodule
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