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verilator/examples/make_tracing_c
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Wilson Snyder 2cad22a22a
Add simulation context (VerilatedContext) (#2660). (#2813) 
**   Add simulation context (VerilatedContext) to allow multiple fully independent
      models to be in the same process.  Please see the updated examples.
**   Add context->time() and context->timeInc() API calls, to set simulation time.
      These now are recommended in place of the legacy sc_time_stamp().
 		2021-03-07 11:01:54 -05:00
..
.gitignore Rename examples in prep for CMake. 2019-10-06 10:32:49 -04:00
Makefile Release examples/Makefiles under CC0. 2020-05-18 22:23:19 -04:00
Makefile_obj Release examples/Makefiles under CC0. 2020-05-18 22:23:19 -04:00
input.vc Rename examples in prep for CMake. 2019-10-06 10:32:49 -04:00
sim_main.cpp Add simulation context (VerilatedContext) (#2660). (#2813) 2021-03-07 11:01:54 -05:00
sub.v Add SPDX license identifiers. No functional change. 2020-03-21 11:24:24 -04:00
top.v Tests: Standardize verilog indentation. 2020-04-05 21:53:24 -04:00