35 lines
784 B
Systemverilog
35 lines
784 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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integer action_hits = 0;
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integer cyc = 0;
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assert property (@(posedge clk) ##1 1'b1)
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action_hits++;
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else
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action_hits--;
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always @(posedge clk) begin
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cyc++;
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assert (0);
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if (cyc == 4) begin
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`checkd(action_hits, 0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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