56 lines
973 B
Systemverilog
56 lines
973 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2024 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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bit clock = 1'b0;
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bit start = 1'b0;
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bit done = 1'b0;
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int concurrent_fails = 0;
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initial begin
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$asserton;
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@(negedge clock);
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start = 1'b1;
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done = 1'b0;
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@(negedge clock);
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start = 1'b0;
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$assertkill;
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$asserton;
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@(posedge clock);
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#1;
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if (concurrent_fails != 0) $stop;
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@(negedge clock);
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start = 1'b1;
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done = 1'b0;
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@(negedge clock);
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start = 1'b0;
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@(posedge clock);
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#1;
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if (concurrent_fails != 1) $stop;
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$assertcontrol(5, 1, 1);
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$asserton;
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$display("%t: finish", $time);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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always #5 clock = ~clock;
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assert_test :
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assert property (@(posedge clock) start |-> ##1 done)
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else concurrent_fails++;
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endmodule
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