verilator/test_regress
Yutetsu TAKATSUKASA d20f22beb1
Fix tristate logic when reading inout port in a module #3399 (#3523)
* Tests: Add a test to reproduce #3399

* Fix #3399. When reading an inout port in a module, it should refer the
original inout port, not the generated MODTEMP.
2022-08-07 21:12:57 +09:00
..
t Fix tristate logic when reading inout port in a module #3399 (#3523) 2022-08-07 21:12:57 +09:00
.gdbinit Delay parsing of associative arrays until dtypes known. 2020-06-09 07:13:40 -04:00
.gitignore Ignore some files generated by modelsim (#2669) 2020-12-05 21:55:56 -05:00
CMakeLists.txt Copyright year update. 2022-01-01 08:26:40 -05:00
Makefile Copyright year update. 2022-01-01 08:26:40 -05:00
Makefile_obj Implement 'forceable' attribute 2022-01-16 15:31:37 +00:00
driver.pl Tests: compare VCD files both ways 2022-07-27 10:48:02 +01:00
input.vc Internal coverage improvements 2020-09-18 21:27:36 -04:00
input.xsim.vc Add XSim support to driver.pl, bug1493. 2019-08-29 17:00:49 -04:00