49 lines
813 B
Systemverilog
49 lines
813 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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interface clk_if;
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bit clk;
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endinterface
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interface inf;
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bit clk;
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bit v;
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clocking cb @(posedge clk);
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inout v;
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endclocking
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endinterface
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class Clocker;
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virtual clk_if clk;
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task clock();
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fork forever #1 clk.clk = ~clk.clk;
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join_none
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endtask
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endclass
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module t;
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clk_if c();
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inf i();
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assign i.clk = c.clk;
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Clocker clocker;
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initial begin
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i.clk = 0;
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i.v = 0;
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clocker = new;
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clocker.clk = c;
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clocker.clock();
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i.cb.v <= 1;
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#5;
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$stop;
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end
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initial @(posedge i.cb.v) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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