Logo
Explore Help
Sign In
luke/verilator
Watch 1
Star 0
Fork 0
mirror of https://github.com/verilator/verilator.git synced 2026-10-06 01:54:01 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
297b297bc7fc4c7cd263fcbacbd27abb99c87a6f
verilator/test_regress
T
History
Yutetsu TAKATSUKASA e8c03650ae Fix internal error if always block without begin-end has concat (#2640) (#2641)
2020-11-13 09:50:09 -05:00
..
t
Fix internal error if always block without begin-end has concat (#2640) (#2641)
2020-11-13 09:50:09 -05:00
.gdbinit
Delay parsing of associative arrays until dtypes known.
2020-06-09 07:13:40 -04:00
.gitignore
Add XSim support to driver.pl, bug1493.
2019-08-29 17:00:49 -04:00
CMakeLists.txt
Add OPT_GLOBAL to use for run-time library (#2373)
2020-05-27 01:52:08 +01:00
driver.pl
Tests: Standard wording.
2020-11-12 18:50:05 -05:00
input.vc
Internal coverage improvements
2020-09-18 21:27:36 -04:00
input.xsim.vc
Add XSim support to driver.pl, bug1493.
2019-08-29 17:00:49 -04:00
Makefile
Clean additional objects.
2020-05-16 13:28:03 -04:00
Makefile_obj
Add SPDX license identifiers. No functional change.
2020-03-21 11:24:24 -04:00
vgen.pl
Make vgen.pl deterministic
2020-04-24 04:53:33 +01:00
Powered by Gitea Version: 1.27.2 Page: 401ms Template: 4ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API