83 lines
2.7 KiB
Systemverilog
83 lines
2.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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integer cyc = 0;
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reg [63:0] crc = '0;
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reg [63:0] sum = '0;
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// Derive test signals from CRC
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wire a = crc[0];
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wire b = crc[1];
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wire c = crc[2];
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wire d = crc[3];
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wire [63:0] result = {60'h0, d, c, b, a};
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always_ff @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b d=%b\n",
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$time, cyc, crc, a, b, c, d);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc == 0) begin
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= '0;
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end else if (cyc < 10) begin
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sum <= '0;
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end else if (cyc == 99) begin
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`checkh(crc, 64'hc77bb9b3784ea091);
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`checkh(sum, 64'hdb7bc8bfe61f987e);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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// =========================================================================
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// Boolean intersect (length-0): equivalent to boolean AND (IEEE 16.9.6)
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// =========================================================================
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// Boolean intersect: when a & b, intersect succeeds (equivalent to AND)
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assert property (@(posedge clk) disable iff (cyc < 2)
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(a & b) |-> (a intersect b));
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// Boolean intersect with constant true -- reduces to just 'a'
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assert property (@(posedge clk) disable iff (cyc < 2)
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a |-> (a intersect 1'b1));
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// =========================================================================
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// Multi-cycle sequence intersect (IEEE 1800-2023 16.9.6)
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// Same-length sequences: intersect succeeds when both arms complete
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// =========================================================================
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// Both arms have length 1; 1'b1 guarantees completion on both sides
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assert property (@(posedge clk)
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(a & b) |-> (a ##1 1'b1) intersect (b ##1 1'b1));
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// Both arms have length 2
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assert property (@(posedge clk)
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(a & b) |-> (a ##2 1'b1) intersect (b ##2 1'b1));
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// Different internal structure, same total length (2 cycles each)
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assert property (@(posedge clk)
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(a & b) |-> (a ##1 1'b1 ##1 1'b1) intersect (b ##2 1'b1));
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// Standalone constant intersect (always passes)
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assert property (@(posedge clk)
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(1'b1 ##1 1'b1) intersect (1'b1 ##1 1'b1));
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endmodule
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