113 lines
1.9 KiB
Systemverilog
113 lines
1.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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reg [3:0] a, b;
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Test1 t1 (
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clk,
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a,
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b
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);
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Test2 t2 (
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clk,
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a,
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b
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);
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Test3 t3 (
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clk,
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a,
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b
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);
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initial begin
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a = 0;
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b = 0;
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end
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always @(posedge clk) begin
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a <= a + 1;
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b = b + 1;
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$display("a = %0d, b = %0d, %0d == %0d", a, b, $sampled(a), $sampled(b));
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if (b >= 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test1 (
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clk,
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a,
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b
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);
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input clk;
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input [3:0] a, b;
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assert property (@(posedge clk) $sampled(a) == $sampled(b));
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endmodule
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module Test2 (
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clk,
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a,
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b
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);
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input clk;
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input [3:0] a, b;
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assert property (@(posedge clk) a == b);
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endmodule
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module Test3 (
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clk,
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a,
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b
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);
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input clk;
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input [3:0] a, b;
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int hits[10];
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assert property (@(posedge clk) a == b) hits[1] = 1;
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assert property (@(posedge clk) a == b)
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else hits[2] = 1;
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assert property (@(posedge clk) a == b) hits[3] = 1;
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else hits[4] = 1;
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assert property (@(posedge clk) a != b) hits[5] = 1;
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assert property (@(posedge clk) a != b)
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else hits[6] = 1;
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assert property (@(posedge clk) a != b) hits[7] = 1;
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else hits[8] = 1;
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final begin
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`checkd(hits[1], 1);
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`checkd(hits[2], 0);
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`checkd(hits[3], 1);
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`checkd(hits[4], 0);
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`checkd(hits[5], 0);
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`checkd(hits[6], 1);
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`checkd(hits[7], 0);
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`checkd(hits[8], 1);
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end
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endmodule
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