88 lines
2.2 KiB
Systemverilog
88 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2019 Peter Monsson
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc;
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initial cyc = 1;
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Test test ( /*AUTOINST*/
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// Inputs
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.clk(clk),
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.cyc(cyc)
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);
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always @(posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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`ifdef TEST_VERBOSE
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$display("cyc=%0d", cyc);
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`endif
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module Test (
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input clk,
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input integer cyc
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);
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`ifdef FAIL_ASSERT_1
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assert property (@(posedge clk) 1 |-> 0)
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else $display("[%0t] wrong implication", $time);
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assert property (@(posedge clk) 1 |=> 0)
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else $display("[%0t] wrong implication", $time);
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assert property (@(posedge clk) cyc % 3 == 1 |=> cyc % 3 == 1)
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else $display("[%0t] wrong implication (step)", $time);
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assert property (@(posedge clk) cyc % 3 == 1 |=> cyc % 3 == 0)
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else $display("[%0t] wrong implication (step)", $time);
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assert property (@(posedge clk) disable iff (cyc == 3) (cyc == 4) |=> 0)
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else $display("[%0t] wrong implication (disable)", $time);
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assert property (@(posedge clk) disable iff (cyc == 6) (cyc == 4) |=> 0)
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else $display("[%0t] wrong implication (disable)", $time);
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`endif
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// Test |->
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assert property (@(posedge clk) 1 |-> 1);
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assert property (@(posedge clk) 0 |-> 0);
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assert property (@(posedge clk) 0 |-> 1);
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// Test |=>
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assert property (@(posedge clk) 1 |=> 1);
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assert property (@(posedge clk) 0 |=> 0);
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assert property (@(posedge clk) 0 |=> 1);
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// Test correct handling of time step in |=>
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assert property (@(posedge clk) cyc % 3 == 1 |=> cyc % 3 == 2);
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// Test correct handling of disable iff
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assert property (@(posedge clk) disable iff ($sampled(cyc) < 3) 1 |=> cyc > 3);
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// Test correct handling of disable iff in current cycle
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assert property (@(posedge clk) disable iff ($sampled(cyc) == 4) (cyc == 4) |=> 0);
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// Test correct handling of disable iff in previous cycle
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assert property (@(posedge clk) disable iff (cyc == 5) (cyc == 4) |=> 0);
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endmodule
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