26 lines
477 B
Systemverilog
26 lines
477 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2018 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// bug1364
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module t (
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input clk,
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input res
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);
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int arr[3];
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initial begin
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arr = '{
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default: '0, //
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1: '0, //
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1: '1
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}; // Bad
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arr = '{'0, '1, '0, '1}; // Bad, too many
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arr = '{'0, '1}; // Bad, too few
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end
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endmodule
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