24 lines
437 B
Systemverilog
24 lines
437 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2018 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// bug1364
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module t ( /*AUTOARG*/
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// Inputs
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clk,
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res
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);
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input clk;
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input res;
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typedef struct packed {logic [3:0] port_num;} info_t;
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info_t myinfo;
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always_comb myinfo = '{default: '0, valids: '1};
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endmodule
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