38 lines
996 B
Systemverilog
38 lines
996 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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localparam string AB = "AB";
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bit r;
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initial begin
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if (('bxz10 ==? 'bxxx0) !== 1) $stop;
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if (('bxz10 ==? 'bxxx1) !== 0) $stop;
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if (('bxz10 ==? 'bx1xx) !== 'x) $stop;
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if (('bxz10 !=? 'bxxx1) !== 1) $stop;
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if (('bxz10 !=? 'bxxx0) !== 0) $stop;
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if (('bxz10 !=? 'b1xx0) !== 'x) $stop;
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r = (AB ==? "AA");
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`checkd(r, 0);
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r = (AB ==? "AB");
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`checkd(r, 1);
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r = (AB !=? "AB");
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`checkd(r, 0);
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// real/shortreal is illegal so not tested here
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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