Wilson Snyder 57c9f22e3c Tests: Enforce 2-space indents on Verilog		2026-06-07 22:00:24 -04:00
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t	Tests: Enforce 2-space indents on Verilog	2026-06-07 22:00:24 -04:00
.gdbinit	…
.gitignore	…
CMakeLists.txt	…
Makefile	…
Makefile_obj	…
driver.py	Apply 'make format'	2026-06-02 20:47:02 +00:00
input.vc	…
input.xsim.vc	…