64 lines
1.7 KiB
Systemverilog
64 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Matthew Ballance
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// SPDX-License-Identifier: CC0-1.0
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// Test querying coverage values via get_inst_coverage
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module t (/*AUTOARG*/);
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/* verilator lint_off UNSIGNED */
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logic [3:0] data;
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covergroup cg;
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coverpoint data {
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bins low = {[0:3]};
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bins mid = {[4:7]};
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bins high = {[8:15]};
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}
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endgroup
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cg cg_inst;
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initial begin
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cg_inst = new;
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// Initially no coverage
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check_coverage(0.0, "initial");
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// Sample low bin - should be 33.33% (1 of 3 bins)
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data = 1;
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cg_inst.sample();
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check_coverage(33.33, "after low");
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// Sample mid bin - should be 66.67% (2 of 3 bins)
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data = 5;
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cg_inst.sample();
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check_coverage(66.67, "after mid");
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// Sample high bin - should be 100% (3 of 3 bins)
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data = 10;
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cg_inst.sample();
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check_coverage(100.0, "after high");
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// Sample again - coverage should still be 100%
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data = 2;
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cg_inst.sample();
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check_coverage(100.0, "after resample");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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task check_coverage(real expected, string label);
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real cov;
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cov = cg_inst.get_inst_coverage();
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$display("Coverage %s: %0.2f%% (expected ~%0.2f%%)", label, cov, expected);
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// Allow 0.5% tolerance for floating point
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if (cov < expected - 0.5 || cov > expected + 0.5) begin
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$error("Coverage mismatch: got %0.2f%%, expected ~%0.2f%%", cov, expected);
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$stop;
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end
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endtask
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endmodule
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