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120 lines
3.6 KiB
Systemverilog
120 lines
3.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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interface Bus #(
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parameter int WIDTH = 1
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);
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logic [WIDTH-1:0] value;
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modport Source(output value);
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endinterface
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typedef virtual Bus #(7).Source SourceBus;
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class Driver;
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extern function void drive_external(virtual Bus bus, logic value);
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extern function void drive_parameter(virtual Bus #(7) bus, logic [6:0] value);
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extern function void drive_modport(virtual Bus #(7).Source bus, logic [6:0] value);
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extern function void drive_array(virtual Bus #(7).Source buses[2], logic [6:0] value);
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extern function void drive_queue(virtual Bus #(7).Source buses[$], logic [6:0] value);
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extern function void drive_dyn(virtual Bus #(7).Source buses[], logic [6:0] value);
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extern function void drive_assoc(virtual Bus #(7).Source buses[int], logic [6:0] value);
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extern function SourceBus get_bus(SourceBus bus);
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function void drive_inline(virtual Bus bus, logic value);
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bus.value = value;
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endfunction
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endclass
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function void Driver::drive_external(virtual Bus bus, logic value);
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bus.value = value;
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endfunction
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function void Driver::drive_parameter(virtual Bus #(7) bus, logic [6:0] value);
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bus.value = value;
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endfunction
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function void Driver::drive_modport(virtual Bus #(7).Source bus, logic [6:0] value);
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bus.value = value;
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endfunction
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function void Driver::drive_array(virtual Bus #(7).Source buses[2], logic [6:0] value);
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buses[1].value = value;
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endfunction
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function void Driver::drive_queue(virtual Bus #(7).Source buses[$], logic [6:0] value);
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buses[1].value = value;
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endfunction
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function void Driver::drive_dyn(virtual Bus #(7).Source buses[], logic [6:0] value);
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buses[1].value = value;
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endfunction
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function void Driver::drive_assoc(virtual Bus #(7).Source buses[int], logic [6:0] value);
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buses[7].value = value;
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endfunction
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function SourceBus Driver::get_bus(SourceBus bus);
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return bus;
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endfunction
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module t;
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Bus bus();
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Bus #(7) parameter_bus();
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Bus #(7) bus_array[2]();
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Driver driver = new;
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initial begin
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automatic SourceBus returned_bus;
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automatic virtual Bus #(7).Source queue_buses[$];
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automatic virtual Bus #(7).Source dyn_buses[];
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automatic virtual Bus #(7).Source assoc_buses[int];
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bus.value = 1'b0;
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driver.drive_inline(bus, 1'b1);
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`checkd(bus.value, 1)
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driver.drive_external(bus, 1'b0);
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`checkd(bus.value, 0)
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driver.drive_parameter(parameter_bus, 7'd31);
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`checkd(parameter_bus.value, 31)
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driver.drive_modport(parameter_bus.Source, 7'd47);
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`checkd(parameter_bus.value, 47)
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driver.drive_array(bus_array, 7'd63);
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`checkd(bus_array[1].value, 63)
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queue_buses.push_back(parameter_bus.Source);
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queue_buses.push_back(bus_array[0].Source);
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driver.drive_queue(queue_buses, 7'd15);
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`checkd(bus_array[0].value, 15)
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dyn_buses = new[2];
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dyn_buses[0] = parameter_bus.Source;
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dyn_buses[1] = bus_array[1].Source;
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driver.drive_dyn(dyn_buses, 7'd23);
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`checkd(bus_array[1].value, 23)
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assoc_buses[7] = parameter_bus.Source;
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driver.drive_assoc(assoc_buses, 7'd39);
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`checkd(parameter_bus.value, 39)
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returned_bus = driver.get_bus(parameter_bus.Source);
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returned_bus.value = 7'd79;
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`checkd(parameter_bus.value, 79)
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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