91 lines
3.9 KiB
C++
91 lines
3.9 KiB
C++
// -*- mode: C++; c-file-style: "cc-mode" -*-
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//*************************************************************************
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// DESCRIPTION: Verilator: Passes over DfgGraph
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//
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// Code available from: https://verilator.org
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//
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//*************************************************************************
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//
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// Copyright 2003-2025 by Wilson Snyder. This program is free software; you
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// can redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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//
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//*************************************************************************
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#ifndef VERILATOR_V3DFGPASSES_H_
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#define VERILATOR_V3DFGPASSES_H_
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#include "config_build.h"
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#include "verilatedos.h"
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#include "V3DfgContext.h"
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class AstModule;
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class DfgGraph;
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namespace V3DfgPasses {
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//===========================================================================
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// Top level entry points
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//===========================================================================
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// Construct a DfGGraph representing the combinational logic in the given AstModule. The logic
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// that is represented by the graph is removed from the given AstModule. Returns the
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// constructed DfgGraph.
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std::unique_ptr<DfgGraph> astToDfg(AstModule&, V3DfgContext&) VL_MT_DISABLED;
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// Same as above, but for the entire netlist, after V3Scope
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std::unique_ptr<DfgGraph> astToDfg(AstNetlist&, V3DfgContext&) VL_MT_DISABLED;
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// Synthesize DfgLogic vertices into primitive operations.
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// Removes all DfgLogic (even those that were not synthesized).
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void synthesize(DfgGraph&, V3DfgContext&) VL_MT_DISABLED;
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// Attempt to make the given cyclic graph into an acyclic, or "less cyclic"
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// equivalent. If the returned pointer is null, then no improvement was
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// possible on the input graph. Otherwise the returned graph is an improvement
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// on the input graph, with at least some cycles eliminated. The returned
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// graph is always independent of the original. If an imporoved graph is
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// returned, then the returned 'bool' flag indicated if the returned graph is
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// acyclic (flag 'true'), or still cyclic (flag 'false').
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std::pair<std::unique_ptr<DfgGraph>, bool> //
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breakCycles(const DfgGraph&, V3DfgContext&) VL_MT_DISABLED;
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// Optimize the given DfgGraph
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void optimize(DfgGraph&, V3DfgContext&) VL_MT_DISABLED;
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// Convert DfgGraph back into Ast, and insert converted graph back into the Ast.
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void dfgToAst(DfgGraph&, V3DfgContext&) VL_MT_DISABLED;
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//===========================================================================
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// Intermediate/internal operations
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//===========================================================================
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// Construct binary to oneHot decoders
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void binToOneHot(DfgGraph&, V3DfgBinToOneHotContext&) VL_MT_DISABLED;
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// Populates the given DfgUserMap for all vertext to:
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// - 0, if the vertex is not part of a non-trivial strongly connected component
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// and is not part of a self-loop. That is: the Vertex is not part of any cycle.
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// - N, if the vertex is part of a non-trivial strongly conneced component or self-loop N.
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// That is: each set of vertices that are reachable from each other will have the same
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// non-zero value assigned.
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// Returns the number of non-trivial SCCs (distinct cycles)
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uint32_t colorStronglyConnectedComponents(const DfgGraph&, DfgUserMap<uint64_t>&) VL_MT_DISABLED;
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// Common subexpression elimination
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void cse(DfgGraph&, V3DfgCseContext&) VL_MT_DISABLED;
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// Inline fully driven variables
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void inlineVars(DfgGraph&) VL_MT_DISABLED;
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// Peephole optimizations
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void peephole(DfgGraph&, V3DfgPeepholeContext&) VL_MT_DISABLED;
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// Regularize graph. This must be run before converting back to Ast.
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void regularize(DfgGraph&, V3DfgRegularizeContext&) VL_MT_DISABLED;
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// Remove unused nodes
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void removeUnused(DfgGraph&) VL_MT_DISABLED;
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// Check all types are consistent. This will not return if there is a type error.
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void typeCheck(const DfgGraph&) VL_MT_DISABLED;
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} // namespace V3DfgPasses
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#endif
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