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https://github.com/verilator/verilator.git
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Geza Lore
8546d5db06
The loops modelling the SystemVerilog scheduling regions are no longer generated. They now live in 'VerilatedEvalLoop' in the runtime library. The generated model holds one as a member, passing itself to it, and exposes each evaluation entry point to it as a pure virtual method on VerilatedModel. The model's 'eval' and 'eval_step' remain the top level entry points, and are backward compatible. V3Sched no longer emits '_eval' or '_eval_settle', etc.. Instead every evaluation entry point called from the runtime is enumerated by 'VEval', Scheduling creates all entry points, for all scheduling regions, even if they are empty, and the runtime eval loop calls everything unconditionally. If regions are empty, this is simply a call to an empty function. This will hurt performance on very small models, but should not be noticeable on anything meaningful, so it is likely best to keep to reduce complexity. A scheduling entry points evaluate a single iteration and returns whether it did any work, they are effectively the previous `_eval_phase_*` functions.
164 lines
6.8 KiB
C++
164 lines
6.8 KiB
C++
// -*- mode: C++; c-file-style: "cc-mode" -*-
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//*************************************************************************
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// DESCRIPTION: Verilator: Block code ordering
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//
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// Code available from: https://verilator.org
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//
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//*************************************************************************
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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//
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//*************************************************************************
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// V3Order's Transformations:
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//
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// Compute near optimal scheduling of always/wire statements
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// Make a graph of the entire netlist
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//
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// For seq logic
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// Add logic_sensitive_vertex for this list of SenItems
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// Add edge for each sensitive_var->logic_sensitive_vertex
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// For AlwaysPre's
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// Add vertex for this logic
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// Add edge logic_sensitive_vertex->logic_vertex
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// Add edge logic_consumed_var_PREVAR->logic_vertex
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// Add edge logic_vertex->logic_generated_var (same as if comb)
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// Add edge logic_vertex->generated_var_PREORDER
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// Cutable dependency to attempt to order dlyed
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// assignments to avoid saving state, thus we prefer
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// a <= b ... As the opposite order would
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// b <= c ... require the old value of b.
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// Add edge consumed_var_POST->logic_vertex
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// This prevents a consumer of the "early" value to be
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// scheduled after we've changed to the next-cycle value
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// For Logic
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// Add vertex for this logic
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// Add edge logic_sensitive_vertex->logic_vertex
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// Add edge logic_generated_var_PREORDER->logic_vertex
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// This ensures the AlwaysPre gets scheduled before this logic
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// Add edge logic_vertex->consumed_var_PREVAR
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// Add edge logic_vertex->consumed_var_POSTVAR
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// Add edge logic_vertex->logic_generated_var (same as if comb)
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// For AlwaysPost's
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// Add vertex for this logic
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// Add edge logic_sensitive_vertex->logic_vertex
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// Add edge logic_consumed_var->logic_vertex (same as if comb)
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// Add edge logic_vertex->logic_generated_var (same as if comb)
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// Add edge consumed_var_POST->logic_vertex (same as if comb)
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//
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// For comb logic
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// For comb logic
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// Add vertex for this logic
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// Add edge logic_consumed_var->logic_vertex
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// Add edge logic_vertex->logic_generated_var
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// Mark it cutable, as circular logic may require
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// the generated signal to become a primary input again.
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//
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//
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//
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// Rank the graph starting at INPUTS (see V3Graph)
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//
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// Visit the graph's logic vertices in ranked order
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// For all logic vertices with all inputs already ordered
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// Make ordered block for this module
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// For all ^^ in same domain
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// Move logic to ordered activation
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// When we have no more choices, we move to the next module
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// and make a new block. Add that new activation block to the list of calls to make.
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//
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//*************************************************************************
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#include "V3PchAstNoMT.h" // VL_MT_DISABLED_CODE_UNIT
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#include "V3OrderInternal.h"
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#include "V3Sched.h"
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#include <memory>
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#include <vector>
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VL_DEFINE_DEBUG_FUNCTIONS;
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void V3Order::orderOrderGraph(OrderGraph& graph, const std::string& tag) {
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// Dump data
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if (dumpGraphLevel()) graph.dumpDotFilePrefixed(tag + "_orderg_pre");
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// Break cycles. Note that the OrderGraph only contains cuttable cycles
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// (soft constraints). Actual logic loops must have been eliminated by
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// the introduction of Hybid sensitivity expressions, before invoking
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// ordering (e.g. in V3SchedAcyclic).
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graph.acyclic(&V3GraphEdge::followAlwaysTrue);
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if (dumpGraphLevel()) graph.dumpDotFilePrefixed(tag + "_orderg_acyc");
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// Assign ranks so we know what to follow, then sort vertices and edges by that ordering
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graph.order();
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if (dumpGraphLevel()) graph.dumpDotFilePrefixed(tag + "_orderg_order");
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}
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//######################################################################
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AstCFunc* V3Order::order(AstNetlist* netlistp, //
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const std::vector<V3Sched::LogicByScope*>& logic, //
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const V3Order::TrigToSenMap& trigToSen,
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const string& tag, //
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bool parallel, //
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bool slow, //
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const ExternalDomainsProvider& externalDomains) {
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// Build the OrderGraph
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const std::unique_ptr<OrderGraph> graph
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= buildOrderGraph(netlistp, logic, trigToSen, parallel);
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// Order it
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orderOrderGraph(*graph, tag);
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// Assign sensitivity domains to combinational logic
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processDomains(netlistp, *graph, tag, externalDomains);
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// Build the move graph
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OrderMoveDomScope::clear();
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const std::unique_ptr<OrderMoveGraph> moveGraphp = OrderMoveGraph::build(*graph, trigToSen);
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if (dumpGraphLevel() >= 9) moveGraphp->dumpDotFilePrefixed(tag + "_ordermv");
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// The ordered statements, if there are any
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AstNodeStmt* stmtsp = nullptr;
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if (!moveGraphp->empty()) {
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if (parallel) {
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stmtsp = createParallel(*moveGraphp, tag, slow);
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} else {
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stmtsp = createSerial(*moveGraphp, tag, slow);
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}
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// Should have consumed all vertices
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UASSERT(moveGraphp->empty(), "Unconsumed vertices remain in OrderMoveGraph");
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}
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OrderMoveDomScope::clear();
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// Dump data
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if (dumpGraphLevel()) graph->dumpDotFilePrefixed(tag + "_orderg_done");
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// Dispose of the remnants of the inputs
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for (auto* const lbsp : logic) lbsp->deleteActives();
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// If there is no resulting logic, then don't create an empty function
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if (!stmtsp) return nullptr;
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// Create the result function
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FileLine* const flp = netlistp->fileline();
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AstCFunc* const funcp = [&]() {
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AstScope* const scopeTopp = netlistp->topScopep()->scopep();
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AstCFunc* const resp = new AstCFunc{flp, "_eval_body__" + tag, scopeTopp, ""};
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resp->dontCombine(true);
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resp->isStatic(false);
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resp->isLoose(true);
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resp->slow(slow);
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resp->isConst(false);
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resp->declPrivate(true);
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scopeTopp->addBlocksp(resp);
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return resp;
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}();
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// Assemble the body
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funcp->addStmtsp(stmtsp);
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// Done
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return funcp;
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}
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