69 lines
1.2 KiB
Systemverilog
69 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty.
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// SPDX-License-Identifier: CC0-1.0
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// multidriven interface test - direct assignment to interface signal and task assign in same process
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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interface my_if;
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logic l0;
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task set_l0_1(); l0 = 1'b1; endtask
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task set_l0_0(); l0 = 1'b0; endtask
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endinterface
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module mod #()(
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input logic sel
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,output logic val
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);
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my_if if0();
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always_comb begin
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if0.l0 = 1'b0;
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if(sel) begin
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if0.set_l0_1();
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end
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end
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assign val = if0.l0;
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endmodule
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module m_tb#()();
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logic sel, val;
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mod m(
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.sel(sel)
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,.val(val)
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);
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initial begin
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#1;
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sel = 'b0;
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`checkd(val, 1'b0);
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#1;
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sel = 'b1;
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`checkd(val, 1'b1);
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#1;
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sel = 'b0;
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`checkd(val, 1'b0);
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#1;
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end
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initial begin
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#5;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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