16 lines
353 B
Systemverilog
16 lines
353 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t(
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input [1:0] i,
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output [1:0] o,
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output [1:0] o2
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);
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wire [1:0] arr [1:0];
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assign o = arr | 1;
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assign o2 = arr | i + 1;
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endmodule
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