verilator/test_regress
Yilou Wang 56ed47ee7c
Fix false ASSIGNIN on interface input port connections (#7365)
* add oneline fix

* Apply 'make format'

* merge test and update 2 space indents

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Co-authored-by: github action <action@example.com>
2026-04-02 20:44:48 +02:00
..
t Fix false ASSIGNIN on interface input port connections (#7365) 2026-04-02 20:44:48 +02:00
.gdbinit
.gitignore
CMakeLists.txt
Makefile Internals: make test-diff macOS compatibility fix - again 2026-01-28 11:05:27 +00:00
Makefile_obj
driver.py Tests: Set MallocNanoZone=0 on macOS when using asan 2026-03-22 17:09:02 +00:00
input.vc
input.xsim.vc