83 lines
2.4 KiB
Systemverilog
83 lines
2.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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localparam int COUNT = 1000;
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int seq;
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int counts[8];
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int sum, hits;
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task prep();
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for (int i = 0; i < COUNT; ++i) counts[i] = 0;
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endtask
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initial begin
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// Single-port and no-port productions
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prep();
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for (int i = 0; i < COUNT; ++i) begin
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randsequence(main)
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main: f_1 f_2 f_3;
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f_1 : func(10);
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f_2 : func(20);
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f_3 : fnoarg;
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void func(int n) : { counts[1] += n; };
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void fnoarg : { ++counts[2]; };
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endsequence
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end
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`checkd(counts[1], COUNT * (10 + 20));
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`checkd(counts[2], COUNT * 1 / 1); // return
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// Multi-port, repeat-with-arg, if-prod-with-arg, nested-prod-with-arg
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sum = 0;
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hits = 0;
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for (int i = 0; i < COUNT; ++i) begin
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// verilog_format: off
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randsequence(main)
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main : multi nested ifcall reps;
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multi : add2(3, 4);
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nested : leaf(7);
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ifcall : if (1) add2(1, 2) else add2(0, 0);
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reps : repeat (3) add2(2, 0);
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void add2(int a, int b) : { sum = sum + a + b; hits = hits + 1; };
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void leaf(int v) : { sum = sum + v; hits = hits + 1; };
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endsequence
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// verilog_format: on
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end
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`checkd(sum, COUNT * (7 + 7 + 3 + 3 * 2));
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`checkd(hits, COUNT * (1 + 1 + 1 + 3));
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// Default port values (IEEE 1800-2023 18.17.7)
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sum = 0;
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hits = 0;
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for (int i = 0; i < COUNT; ++i) begin
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// verilog_format: off
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randsequence(main)
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main : useDefault override1 override2;
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useDefault : add_def;
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override1 : add_def(50);
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override2 : add_def(100);
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void add_def(int n = 7) : { sum = sum + n; hits = hits + 1; };
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endsequence
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// verilog_format: on
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end
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`checkd(sum, COUNT * (7 + 50 + 100));
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`checkd(hits, COUNT * 3);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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