105 lines
3.0 KiB
Systemverilog
105 lines
3.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`ifdef verilator
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`define no_optimize(v) $c(v)
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`else
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`define no_optimize(v) (v)
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`endif
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// verilog_format: on
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// verilator lint_off MULTIDRIVEN
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interface ifc;
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wire [1:0] w;
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// Self-contained interface-internal tristate driver: 'z while en==0, so any
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// external driver must win the net resolution. no_optimize keeps the driver
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// values from being constant-folded, so the resolution runs at run time.
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logic en;
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logic [1:0] wint;
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assign en = `no_optimize(1'b0);
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assign wint = `no_optimize(2'b11);
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assign w = en ? wint : 2'bzz;
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// Read the resolved net from inside the interface (a consumer's view), so the
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// check sees the true resolution, not the driving module's own local copy.
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function automatic logic [1:0] get_w();
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return w;
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endfunction
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endinterface
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// Interface net made tristate only by an external 'z driver (no internal driver).
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interface ifc_tri;
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tri [1:0] w;
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endinterface
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module driver (
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ifc io,
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input logic [1:0] din
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);
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// Plain (non-Z) cross-hierarchy driver of an interface tristate net.
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// This module's own tristate graph has no 'z on io.w, so before the fix this
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// contribution was silently dropped and io.w resolved to the interface-internal
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// 'z (== 0) only.
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assign io.w = din;
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endmodule
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module driver_tri (
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ifc_tri io,
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input logic [1:0] din
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);
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assign io.w = din;
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endmodule
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module zdriver (
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ifc_tri io
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);
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assign io.w = 2'bzz;
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endmodule
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module t;
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// u_a, u_b: interface nets driven plainly from the top module (depth-0 xref).
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// u_c: interface net driven plainly from a child module (depth-1 xref).
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ifc u_a ();
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ifc u_b ();
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ifc u_c ();
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// u_e: net is tristate only via zdriver's external 'z; the plain driver must
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// still win (the interface itself has no internal driver).
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ifc_tri u_e ();
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logic [1:0] va, vb, vc, ve;
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assign va = `no_optimize(2'b01);
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assign vb = `no_optimize(2'b10);
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assign vc = `no_optimize(2'b11);
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assign ve = `no_optimize(2'b01);
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assign u_a.w = va; // plain top-level driver
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assign u_b.w = vb; // plain top-level driver
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driver u_drv (
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.io(u_c),
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.din(vc)
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); // plain driver in a child module
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driver_tri u_pdrv (
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.io(u_e),
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.din(ve)
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); // plain driver of an externally-tristated net
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zdriver u_zdrv (.io(u_e)); // external 'z driver
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initial begin
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#1;
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// The plain external driver must win over the interface-internal 'z.
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`checkh(u_a.get_w(), 2'b01);
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`checkh(u_b.get_w(), 2'b10);
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`checkh(u_c.get_w(), 2'b11);
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// The plain driver must win over an external-only 'z (no internal driver).
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`checkh(u_e.w, 2'b01);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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