15 lines
357 B
Systemverilog
15 lines
357 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2003 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define foo bar
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`ifdef foo
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`ifdef baz `else
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// Test file to make sure includes work;
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integer user_loaded_value;
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`endif
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`endif
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