158 lines
2.6 KiB
Systemverilog
158 lines
2.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module rr #(
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) (
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input logic clk,
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input logic rst,
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input logic [7:0] data,
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input logic data_q
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);
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logic a;
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logic [15:0] dcnt;
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typedef enum logic [7:0] {
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S0,
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S1,
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S2,
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S3
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} state_t;
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state_t state_d, state_q;
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always_ff @(posedge clk or negedge rst) if (!rst) state_q <= S0;
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always_ff @(posedge clk)
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unique case (state_q)
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S1: if (a) dcnt[7:0] <= data;
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S2: if (a) dcnt[15:8] <= data;
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S3: if (data_q) dcnt <= dcnt - 1;
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default: dcnt <= dcnt;
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endcase
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endmodule
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module re #(
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) (
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input logic clk,
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input logic rst,
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output logic o,
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input unused0, /* block optimizations */
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input unused1,
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input unused2,
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input unused3,
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input unused4,
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input unused5,
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input unused6,
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input unused7,
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input unused8,
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input unused9,
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input unused10,
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input unused11,
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input unused12,
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input unused13,
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input unused14,
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input unused15,
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input unused16,
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input unused17,
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input unused18,
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input unused19,
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input unused20,
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input unused21,
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input unused22,
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input unused23,
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input unused24,
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input unused25,
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input unused26,
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input unused27,
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input unused28,
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input unused29,
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input unused30,
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input unused31,
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input unused32,
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input unused33,
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input unused34,
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input unused35,
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input unused36,
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input unused37,
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input unused38,
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input unused39,
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input unused40
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);
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logic [15:0] dcnt;
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typedef enum logic [7:0] {
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S0,
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S1
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} state_t;
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state_t state_d, state_q;
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always_ff @(posedge clk or negedge rst) if (!rst) state_q <= S0;
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always_ff @(posedge clk)
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unique case (state_q)
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S1: o <= dcnt[0];
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default: o <= '0;
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endcase
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module rh #(
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) (
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input logic clk
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);
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logic [7:0] a;
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logic b;
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logic c;
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logic d;
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logic rst;
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rr xrr (
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.clk,
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.rst(rst),
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.data(a),
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.data_q(b & c)
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);
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re xre (
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.clk,
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.rst(rst),
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.o(d)
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);
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endmodule
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module U #(
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) (
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input clk,
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input rst
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);
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rh xrh (.clk(clk));
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endmodule
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module C #(
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) (
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input clk,
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input rst
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);
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U U (
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.clk,
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.rst
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);
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endmodule
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module A #() ();
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logic clk;
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logic rst;
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C c0 (
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.clk,
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.rst
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);
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C c1 (
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.clk,
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.rst
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);
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endmodule
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module B #() ();
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logic clk;
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logic rst;
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C xC (
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.clk,
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.rst
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);
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endmodule
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module t #() ();
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B b ();
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A a ();
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endmodule
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