132 lines
3.6 KiB
Systemverilog
132 lines
3.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Nikolai Kumar
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// SPDX-License-Identifier: CC0-1.0
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`define checkh(g,e) do if ((g) !==(e)) begin $write("%%Error: %s:%0d: got=%b exp=%b\n", `__FILE__,`__LINE__, (g),(e)); $stop; end while(0)
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module t (
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input clk
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);
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int cyc = 0;
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always @(posedge clk) cyc <= cyc + 1;
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logic [4:1] var_arr [2];
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/* verilator lint_off ASCRANGE */
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logic [1:4] var_arr_a [2];
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/* verilator lint_on ASCRANGE */
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logic [72:1] wide_arr [2];
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always @(posedge clk) begin
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var_arr[0] <= 4'b0101;
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var_arr[1] <= (cyc <= 3) ? 4'b1111 : (cyc <= 7) ? 4'b0000 : 4'b0001;
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var_arr_a[0] <= 4'b1010;
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var_arr_a[1] <= 4'b0000;
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wide_arr[0] <= '0;
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wide_arr[1] <= 72'hAB_CDEF0123_456789AB;
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end
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always @(posedge clk) begin
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if (cyc == 2) force var_arr[1][1] = 1'b0;
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if (cyc == 6) force var_arr[1][4] = 1'b1;
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if (cyc == 8) release var_arr[1][1];
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if (cyc == 10) force var_arr[1] = 4'b1010;
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if (cyc == 12) release var_arr[1];
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if (cyc == 2) force wide_arr[1][36:5] = 32'hffff_ffff;
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if (cyc == 4) release wide_arr[1];
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if (cyc == 2) force var_arr_a[1][2:4] = 3'b111;
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if (cyc == 4) force var_arr_a[1][3]= 1'b0;
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if (cyc == 6) release var_arr_a[1];
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if (cyc == 7) force var_arr_a[1][3:4] = 2'b11;
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if (cyc == 9) force var_arr_a[1][2:3]= 2'b00;
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if (cyc == 11) release var_arr_a[1];
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if (cyc == 12) force var_arr_a[1][1:2] = 2'b11;
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if (cyc == 14) force var_arr_a[1][2:3]= 2'b00;
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if (cyc == 16) release var_arr_a[1];
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if (cyc == 17) force var_arr_a[1][2:3] = 2'b11;
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if (cyc == 19) force var_arr_a[1][1:3]= 3'b000;
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if (cyc == 21) release var_arr_a[1];
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if (cyc == 14) force var_arr[1][1] = 1'b0;
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if (cyc == 14) force var_arr[0][1] = 1'b0;
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if (cyc == 16) release var_arr[1][1];
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if (cyc == 16) release var_arr[0][1];
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if (cyc == 18) force var_arr[0] = 4'b1010;
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if (cyc == 20) force var_arr[0][1] = 1'b1;
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if (cyc == 22) release var_arr[0];
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end
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always @(posedge clk) case (cyc)
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1: begin
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`checkh(var_arr[0], 4'b0101);
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`checkh(var_arr[1], 4'b1111);
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end
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3: begin
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`checkh(var_arr[1], 4'b1110);
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`checkh(wide_arr[1][36:5], 32'hffff_ffff);
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`checkh(wide_arr[1][4:1], 4'hB);
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`checkh(wide_arr[1][72:37], 36'hABCDEF012);
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`checkh(var_arr_a[1], 4'b0111);
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`checkh(var_arr_a[0], 4'b1010);
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end
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5: begin
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`checkh(var_arr[1], 4'b0000);
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`checkh(wide_arr[1], 72'hAB_CDEF0123_456789AB);
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`checkh(var_arr_a[1], 4'b0101);
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end
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7: begin
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`checkh(var_arr[1], 4'b1000);
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end
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8: begin
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`checkh(var_arr_a[1], 4'b0011);
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end
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9: begin
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`checkh(var_arr[1], 4'b1001);
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end
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10: begin
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`checkh(var_arr_a[1], 4'b0001);
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end
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11: begin
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`checkh(var_arr[1], 4'b1010);
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`checkh(var_arr[0], 4'b0101);
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end
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13: begin
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`checkh(var_arr[1], 4'b0001);
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`checkh(var_arr_a[1], 4'b1100);
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end
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15: begin
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`checkh(var_arr_a[1], 4'b1000);
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`checkh(var_arr[1], 4'b0000);
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`checkh(var_arr[0], 4'b0100);
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end
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17: begin
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`checkh(var_arr[1], 4'b0001);
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`checkh(var_arr[0], 4'b0101);
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end
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18: begin
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`checkh(var_arr_a[1], 4'b0110);
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end
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19: begin
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`checkh(var_arr[0], 4'b1010);
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end
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20: begin
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`checkh(var_arr_a[1], 4'b0000);
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end
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21: begin
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`checkh(var_arr[0], 4'b1011);
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end
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22: begin
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`checkh(var_arr_a[1], 4'b0000);
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end
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23: begin
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`checkh(var_arr[0], 4'b0101);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endcase
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endmodule
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