34 lines
809 B
Systemverilog
34 lines
809 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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// 9-Jun-2026: Modifications for this test contributed by Yilin Li.
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export "DPI-C" task readHEX;
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export "DPI-C" task loadHEX;
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task readHEX;
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input string file;
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output logic [7:0] stimuli[32'h00010000];
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$readmemh(file, stimuli);
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endtask
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task loadHEX;
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input string file;
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logic [7:0] stimuli[32'h00010000];
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readHEX(file, stimuli);
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endtask
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module tb ();
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logic [7:0] result[32'h00010000];
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initial begin
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loadHEX("dummy");
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end
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endmodule
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