36 lines
1015 B
Systemverilog
36 lines
1015 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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logic a, b, c;
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default clocking cb @(posedge clk);
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endclocking
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// cover sequence (IEEE 1800-2023 16.14.3) counts every end-of-match. The
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// following forms put a sub-sequence where only its final end is forwarded,
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// so they are ignored (COVERIGN) rather than under-counted.
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// Sequence operand of 'or' (ranged cycle delay).
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cover sequence ((a ##[1:3] b) or 1'b0);
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// Sequence operand of 'or' (consecutive repetition).
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cover sequence ((a [* 1: 3]) or 1'b0);
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// Ranged cycle delay before a multi-cycle sequence.
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cover sequence (a ##[1:2] (b ##1 c));
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// Ranged cycle delay wide enough to use the counter FSM.
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cover sequence (a ##[1:300] b);
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// Ranged goto repetition (every M..N-th match is a separate end).
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cover sequence (a [-> 2: 3]);
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endmodule
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