91 lines
3.2 KiB
Systemverilog
91 lines
3.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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logic [63:0] crc = 64'h5aef0c8dd70a4497;
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logic rst_n = 1'b0;
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logic a, b, c, d, e;
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int cyc = 0;
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int hit_simple = 0;
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int hit_clocked = 0;
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int hit_clocked_disable = 0;
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int hit_default_disable = 0;
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int hit_consrep_range = 0;
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int hit_consrep_2 = 0;
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int hit_consrep_3 = 0;
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default clocking cb @(posedge clk);
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endclocking
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// Non-adjacent CRC bits to avoid LFSR shift correlation
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assign a = crc[0];
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assign b = crc[5];
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assign c = crc[10];
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assign d = crc[15];
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assign e = crc[20];
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// Form 1: cover sequence ( sexpr ) stmt
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cover sequence (a | b | c | d | e) hit_simple++;
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// Form 2: cover sequence ( clocking_event sexpr ) stmt
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cover sequence (@(posedge clk) (a | b | c | d | e) ##[1:3] b) hit_clocked++;
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// Form 3: cover sequence ( clocking_event disable iff (expr) sexpr ) stmt
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cover sequence (@(posedge clk) disable iff (!rst_n) a ##1 b) hit_clocked_disable++;
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// Form 4: cover sequence ( disable iff (expr) sexpr ) stmt
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cover sequence (disable iff (!rst_n) a ##1 c) hit_default_disable++;
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// Form 5: consecutive repetition, counted per end-of-match
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cover sequence (a [* 2: 3]) hit_consrep_range++;
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cover sequence (a [* 2]) hit_consrep_2++;
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cover sequence (a [* 3]) hit_consrep_3++;
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc=%0d crc=%x a=%b b=%b c=%b d=%b e=%b\n", $time, cyc, crc, a, b, c, d, e);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[1] ^ crc[0]};
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if (cyc == 2) rst_n <= 1'b1;
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if (cyc == 99) begin
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`checkh(crc, 64'h261a9f1371d7aadf);
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$finish;
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end
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end
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// Read the counters in 'final', not the clocked block: a same-cycle read of a
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// cover counter races the cover's increment under --threads (vltmt). Verilator
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// counts one more end-of-match than Questa 2022.3 on some forms at the
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// simulation boundary; the Questa value is noted per check.
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final begin
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`ifdef TEST_VERBOSE
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$write("simple=%0d clocked=%0d clk_dis=%0d def_dis=%0d range=%0d 2=%0d 3=%0d\n", hit_simple,
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hit_clocked, hit_clocked_disable, hit_default_disable, hit_consrep_range, hit_consrep_2,
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hit_consrep_3);
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`endif
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`checkd(hit_simple, 96); // Questa: 95
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`checkd(hit_clocked, 149); // Questa: 149
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`checkd(hit_clocked_disable, 28); // Questa: 27
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`checkd(hit_default_disable, 30); // Questa: 30
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`checkd(hit_consrep_2, 30); // Questa: 29
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`checkd(hit_consrep_3, 14); // Questa: 13
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// a[*2:3] == a[*2] or a[*3] (IEEE 1800-2023 16.9.2)
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`checkd(hit_consrep_range, hit_consrep_2 + hit_consrep_3); // 44; Questa: 42
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$write("*-* All Finished *-*\n");
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end
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endmodule
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