58 lines
1.5 KiB
Systemverilog
58 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Regression: a `priority` case item whose later condition (INST_B) is fully
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// subsumed by an earlier condition (INST_A) of the *same* item. Overlap within
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// a single case item is legal, but this previously crashed V3Case with a null
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// pointer dereference: the priority "case item ignored" CASEOVERLAP diagnostic
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// dereferenced 'overlappedCondp', which is null when the only covering item is
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// the item itself. Must compile cleanly and simulate correctly.
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t;
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logic clk = 1'b0;
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always #5 clk = ~clk;
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logic [1:0] in;
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logic [1:0] out;
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always_comb begin
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priority casez (in)
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2'b1?, // fully subsumes 2'b11 below on the same case clause
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2'b11:
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out = 2'b10;
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2'b0?: out = 2'b01;
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endcase
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end
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initial begin
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in = 2'b00;
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@(posedge clk);
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`checkh(out, 2'b01);
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in = 2'b01;
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@(posedge clk);
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`checkh(out, 2'b01);
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in = 2'b10;
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@(posedge clk);
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`checkh(out, 2'b10);
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in = 2'b11;
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@(posedge clk);
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`checkh(out, 2'b10);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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