48 lines
1.2 KiB
Systemverilog
48 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module top;
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bit clk = 1'b0;
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always #1 clk = ~clk;
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logic [2:0] cyc = 3'd0;
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int count = 0;
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always @(posedge clk) begin
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// verilator lint_off CASEWITHX
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case (cyc) inside
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3'b000: begin
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$display("case inside 000");
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++count;
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end
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3'b001: begin
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$display("case inside 001");
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++count;
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end
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// Should match z
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3'b01?: begin
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$display("case inside 01?");
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++count;
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end
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// Should match x
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3'b1xx: begin
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$display("case inside 1xx");
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++count;
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end
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endcase
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// verilator lint_on CASEWITHX
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cyc <= cyc + 3'd1;
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if (&cyc) begin
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`checkh(count, 8);
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$finish;
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end
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end
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endmodule
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