37 lines
660 B
Systemverilog
37 lines
660 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk,
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input clk2
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);
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logic a, b;
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// verilog_format: off
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sequence s_multi;
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@(posedge clk) a;
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endsequence
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sequence s_nest;
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@(posedge clk) b;
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endsequence
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sequence s_level;
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@clk a;
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endsequence
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sequence s_level2;
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@clk a
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endsequence
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// verilog_format: on
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assert property (@(posedge clk2) s_multi);
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assert property (s_nest ##1 a);
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assert property (s_level);
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assert property (s_level2);
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endmodule
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